Implementation of Coarse Frequency Estimation Algorithm in FPGA as a part of Software Defined Radio Receiver

Software Defined Radio (SDR) is one of the most emerging technologies of communication industry. It has the ability to adapt itself to the environment and can be designed to operate in extremely hostile environment. Its major advantage comes from the fact that the algorithms implemented to facilitate communication are reconfigurable by the software. At the same time, to meet the processing requirements of computationally complex algorithms, a target technology of FPGA can be used to implement them. The acquisition of frequency from the received signal is a key to the demodulation process in SDR. In this paper, we have presented the design of Coarse Frequency Estimation Algorithm and implemented in FPGA.